Intel is set to showcase its PowerVia technology at the VLSI Symposium 2023, which will take place from June 11-16. The technology will be demonstrated on an E-Core chip built using the Intel 4 node. Unlike conventional chips, PowerVia technology dedicates specific layers for power delivery, effectively separating them from the signal routing layers. This approach allows for vertical power delivery through a set of power-specific Through-Silicon Vias (TSVs) or PowerVias, which are essentially vertical connections between the top and bottom surfaces of the chip. By delivering power directly from the backside of the chip, PowerVia reduces power supply noise and resistive losses, optimizing power distribution and improving overall energy efficiency.
Intel has prepared a paper for the VLSI Symposium 2023, which highlights a design made using Intel 4 technology and implements E-Cores only in a test chip. The paper states that PowerVia technology is a novel innovation to extend process scaling by having power delivery on the backside. The technology enabled standard cell utilization of greater than 90 percent in large areas of the core while showing greater than 5 percent frequency benefit in silicon due to reduced IR drop. Successful post-silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristics of the PowerVia test chip are in line with higher power densities expected from logic scaling.
PowerVia provides better frequency and reduced IR drop, and thermal management is a significant benefit as well. As logic scaling continues, more transistors are packed in a smaller space, increasing the thermal density. PowerVias should allow that to be a smaller problem and help heat escape more efficiently. Although PowerVia is scheduled for the Intel 20A node, the company implemented it for Intel 4 node to learn and present how it works and how it is implemented to Intel Foundry Service (IFS) customers.
